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Q#1
Sequential Circuits
GATE EC 2003
MCQ
+2 marks
-0.66 marks
A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
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Browse Practice Questions by Chapters / Topics in Browse Practice Questions by Chapters / Topics in GATE Electronics and Communications
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| Topic | Questions | Attempted | Correct | |
|---|---|---|---|---|
| Network Analysis | 273 | 0 | 0 | |
| Electronic Devices | 69 | 0 | 0 | |
| Analog Electronics | 395 | 0 | 0 | |
| Digital Electronics | 351 | 0 | 0 | |
| Signals and Systems | 22 | 0 | 0 | |
| Control Systems | 224 | 0 | 0 | |
| Communication System | 200 | 0 | 0 | |
| EMFT - ECE | 14 | 0 | 0 | |
| Engineering Mathematics | 24 | 0 | 0 | |
| General Aptitude | 30 | 0 | 0 |