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Q#1
Sequential Circuits
GATE EC 2017
MCQ
+2 marks
-0.66 marks
A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are
Assume that is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state and clocked, after a few clock cycles, it starts cycling through
all of the four possible states if
three of the four possible state if
only two of the four possible states if
only two of the four possible states if
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| Topic | Questions | Attempted | Correct | |
|---|---|---|---|---|
| Network Analysis | 273 | 0 | 0 | |
| Electronic Devices | 69 | 0 | 0 | |
| Analog Electronics | 395 | 0 | 0 | |
| Digital Electronics | 351 | 0 | 0 | |
| Signals and Systems | 22 | 0 | 0 | |
| Control Systems | 224 | 0 | 0 | |
| Communication System | 200 | 0 | 0 | |
| EMFT - ECE | 14 | 0 | 0 | |
| Engineering Mathematics | 24 | 0 | 0 | |
| General Aptitude | 30 | 0 | 0 |