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Q#1
Sequential Circuits
GATE EC 1993
NAT
+2 marks
-0 marks
A pulse train with a frequency of 1 MHz is counted using a modulo 1024 ripple counter built with J-K flip flops. For proper operation of the counter, the maximum permissible propagation delay per flip flop stage is _______n sec.
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| Topic | Questions | Attempted | Correct | |
|---|---|---|---|---|
| Network Analysis | 273 | 0 | 0 | |
| Electronic Devices | 69 | 0 | 0 | |
| Analog Electronics | 395 | 0 | 0 | |
| Digital Electronics | 351 | 0 | 0 | |
| Signals and Systems | 22 | 0 | 0 | |
| Control Systems | 224 | 0 | 0 | |
| Communication System | 200 | 0 | 0 | |
| EMFT - ECE | 14 | 0 | 0 | |
| Engineering Mathematics | 24 | 0 | 0 | |
| General Aptitude | 30 | 0 | 0 |