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Q#1
Logic Family
GATE EC 2019
MCQ
+1 mark
-0.33 marks
A standard CMOS inverter is designed with equal rise and fall times. If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise marginand the HIGH noise margin?
decreases andincreases
Bothandincrease
No change in the noise margin
increases anddecreases
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Browse Practice Questions by Chapters / Topics in Browse Practice Questions by Chapters / Topics in GATE Electronics and Communications
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| Topic | Questions | Attempted | Correct | |
|---|---|---|---|---|
| Network Analysis | 273 | 0 | 0 | |
| Electronic Devices | 69 | 0 | 0 | |
| Analog Electronics | 395 | 0 | 0 | |
| Digital Electronics | 351 | 0 | 0 | |
| Signals and Systems | 22 | 0 | 0 | |
| Control Systems | 224 | 0 | 0 | |
| Communication System | 200 | 0 | 0 | |
| EMFT - ECE | 14 | 0 | 0 | |
| Engineering Mathematics | 24 | 0 | 0 | |
| General Aptitude | 30 | 0 | 0 |