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Q#1
Microprocessor
GATE EC 2007
MCQ
+2 marks
-0.66 marks
An 8255 chip is interfaced to an 8085 microprocessor system as an I/O mapped I/O as shown in the figure. The address lines and of the 8085 are used by the 8255 chip to decode internally its three ports and the Control register. The address lines. to as well as signal are used for address decoding. The range of addresses for which the 8255 chip would get selected is
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Browse Practice Questions by Chapters / Topics in Browse Practice Questions by Chapters / Topics in GATE Electronics and Communications
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| Topic | Questions | Attempted | Correct | |
|---|---|---|---|---|
| Network Analysis | 273 | 0 | 0 | |
| Electronic Devices | 69 | 0 | 0 | |
| Analog Electronics | 395 | 0 | 0 | |
| Digital Electronics | 351 | 0 | 0 | |
| Signals and Systems | 22 | 0 | 0 | |
| Control Systems | 224 | 0 | 0 | |
| Communication System | 200 | 0 | 0 | |
| EMFT - ECE | 14 | 0 | 0 | |
| Engineering Mathematics | 24 | 0 | 0 | |
| General Aptitude | 30 | 0 | 0 |