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Q#1
Sequential Circuits
GATE EC 2025
NAT
+2 marks
-0 marks
In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2 ns.
The maximum clock frequency (in MHz, rounded off to the nearest integer) such that there are no setup violations is ________
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| Topic | Questions | Attempted | Correct | |
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| Network Analysis | 273 | 0 | 0 | |
| Electronic Devices | 69 | 0 | 0 | |
| Analog Electronics | 395 | 0 | 0 | |
| Digital Electronics | 351 | 0 | 0 | |
| Signals and Systems | 22 | 0 | 0 | |
| Control Systems | 224 | 0 | 0 | |
| Communication System | 200 | 0 | 0 | |
| EMFT - ECE | 14 | 0 | 0 | |
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| General Aptitude | 30 | 0 | 0 |