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Q#1
Logic Family
GATE EC 1999
NAT
+2 marks
-0 marks
In the CMOS inverter circuit shown in Figure, the input makes a transition from to . Determine the high-to-low propagation delay time (μsec). when it is driving capacitance load of 20pF. Device data:
NMOS: ; , ,
PMOS: ; , .
Neglect body effect.
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| Topic | Questions | Attempted | Correct | |
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| Network Analysis | 273 | 0 | 0 | |
| Electronic Devices | 69 | 0 | 0 | |
| Analog Electronics | 395 | 0 | 0 | |
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| Signals and Systems | 22 | 0 | 0 | |
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| EMFT - ECE | 14 | 0 | 0 | |
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| General Aptitude | 30 | 0 | 0 |