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Q#1
Sequential Circuits
GATE EC 2017
NAT
+2 marks
-0 marks
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in figure. The FSM has an input ‘In’ and an output ‘Out’. The initial state of the FSM is .
If the input sequence is 10101101001101, starting with the left-most bit, then the number of times will be 1 is ____
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| Topic | Questions | Attempted | Correct | |
|---|---|---|---|---|
| Network Analysis | 273 | 0 | 0 | |
| Electronic Devices | 69 | 0 | 0 | |
| Analog Electronics | 395 | 0 | 0 | |
| Digital Electronics | 351 | 0 | 0 | |
| Signals and Systems | 22 | 0 | 0 | |
| Control Systems | 224 | 0 | 0 | |
| Communication System | 200 | 0 | 0 | |
| EMFT - ECE | 14 | 0 | 0 | |
| Engineering Mathematics | 24 | 0 | 0 | |
| General Aptitude | 30 | 0 | 0 |