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Q#1
Combinational Circuits
GATE EE 2014
MCQ
+1 mark
-0.33 marks
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where X is the don’t care condition, and Q is the output representing the state.
The logic gate represented by the gate diagram is
XOR
OR
AND
NAND
Explanation:
This is the truth table of the gate mentioned in the diagram. From the truth table, we can see that the gate is clearly NAND Gate.
Note: While deriving the truth table no need to look at the state, we just need to focus on input-output combination.
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