MOV R0, 0 × 60 ← (60)H is stored in R0

MOV R1, 0 × 46 ← (46)H is stored in R1

ADD R0, R1

Both values get added

Number of 1’s in result = 4 = even ∴ P =0

Overflow bit is 1 because both numbers have MSB = 0 i.e. positive numbers but result has MSB = 1 i.e. negative number.

CAOP = 0010; decimal value = 2

LX1 H, 2001 H                HL = (2001)H

MVI A, 21 H                 A = (21)H

INXH                                HL = (2002)H

ADD M                        A = A + M = 21 + B1 = (D2)H

INXH                                HL = (2003)H

MOV M, A                (2003)H ← (D2)H = (210)10 

HLT

When CALL instruction is executed the address of LP is pushed to the top of stack and then the PC is fed with new address. To return the execution to LP + DISP + 3.

The address of LP must be extracted in HL register pair by means of POP instruction and then DISP is added to it by the use of DAD instruction so that HL = LP +DISP

Then HL register pair is incremented thrice to obtain HL = LP +DISP + 3

Then this is pushed back to the top of stack to be fed to Program Counter upon execution of RET instruction.

Whenever a CALL instruction is executed then the address of next instruction i.e. the contents of Program Counter are pushed to the Stack.

Then the Stack Pointer is incremented to point to the next memory location but in actual Stack Pointer is decremented.

Then the new address is stored in Program Counter to shift the program execution to  anew location.

XRA A: clear the contents of Accumulator. A = 00H

MVI B F0H;    B = F0H

SUB B; A =A – B

A =      0000 0000

B =      1111 0000

A –B = 0001 0000 = (10)H and CY will be 1 as carry acts as borrow in case of subtraction.

Memory Mapped I/O are accessed as memory location and to access a memory location, its address must be stored in HL register pair so, the first instruction should be

LXI H, 2500H

Now, the data from this address can be directly moved to accumulator by using the instruction,

MOV A, M

DAD SP : Add the contents of SP register to the HL register pair and store the result in HL register pair.

HL = HL + SP = 2700H

PCHL: Load the Program Counter with the contents of HL register pair.

PC = HL = 2700H

Hence, after execution of these instructions the contents of both SP and PC is 2700H.

The INT pin is sampled after every machine cycle that is its value is sampled even in between execution of an instruction.

The BRQ or Bus Request Pin is sampled after every instruction cycle i.e. on completion of execution of an instruction.

The given number is (11010110)2 = (214)10

Since, it is in 2’s complement form, the actual number is 28 -  214 = (42)10

When this number is divided by 2 the result is (21)10

This number can be expressed in 2’s complement form as, 28 -  21 = (235)10

(235)10 = (11101011)2

The objective of instruction sequence is to convert (11010110)2 to (11101011)2 by the use of Shift Instructions.

L2 : 11010110 -> 10101101,         CY = 1

R2: 10101101 -> 11010110,        CY = 1

R1: 11010110 -> 11101011,        CY = 0

Note:  Here, we must verify the options in order to know the correct sequence.

In the first iteration, the value of register L is decremented from 25510 to 010. So, DCR L is executed 255 times.

In rest of 254 iterations the value of register L is decremented from 00H to 00H i.e. the value is decremented 256 times.

Hence, DCR L instruction is executed = 255 + 254 x 256 = 65,279 times

First XCHG instruction must be executed to transfer the memory address from DE register pair to HL register pair.

Then we can use INR M instruction to increase the content of memory location pointed to by HL register pair.

SPHL Instruction copies the content of HL register pair into the Stack Pointer register.

STAX copies the content of accumulator into the memory location whose address is specified by the operand register pair.

SHLD is used to copy the contents of HL register pair in the memory location specified.

SHLD 2050H copies contents of H in the memory location 2050H and L into 2051H.

Both MVI and RLC instruction do not affect the zero flag so it will remain as it is. Hence, we can safely assume that all instructions will be executed once.

Since, there are a total of 4 instruction so it requires 4 instruction cycles to operate.

Program Counter contains the address of next instruction to be executed.

Since, there are 4 data lines in each memory chip, it means that each memory register is 4 bits wide.

Number of Address Lines = 12

Total number of memory location in each chip =  

Number of bits that can be stored =

Total bits in 8 memory chips =

8 bits = 1 byte

Total Size =

So, the result is stored at 1F00H.

Since, the CS signals is an active low signal so the output of NAND Gate must be 0 to assert the Chip Select signal. Hence, all inputs must be asserted to make the output zero.

Since, A12 is associated with an inverter, it must be LOW to be asserted.

A15 = 1, A14 = 1, A13 = 1, A12 = 0.

Minimum Address = 1110 0000 0000 0000  (E000 H)

Maximum Address = 1110 1111 1111 1111  (EFFF H)

The instruction NOP will be executed as many number of times as the loop is executed. Upon execution once,

A = A + B = 20H (0010 0000)

RLC;  A = 40H     (0100 0000), CY = 0

Second execution,

A = A + B = 50H  (0101 0000)

RLC; A = A0H       (1010 0000), CY = 0

Third execution,

A = A + B = B0H  (1011 0000)

RLC; A = 61H        (0110 0001), CY = 1

Since, the CY flag is now set the loop terminates and hence NOP instruction is executed thrice.

TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts whereas INTR is a non-vectored interrupt.

Program Counter stores the address of next instruction to be executed.

Assembler converts program written in High Level Language to Machine code with one line at a time.

For CS to be selected all the address lines connected to AND Gate should be asserted so

(A11 – 1, A12 – 1, A13 – 1, A14 – 1, A15 – 1).

The other address lines can vary from all 0’s and all 1’s. Hence the address range can vary between

Minimum Address: 1111 1000 0000 0000 = (F800 H)

Maximum Address: 1111 1111 1111 1111 = (FFFF H)

ANA r: ANDs the content of register with accumulator which modifies the content of accumulator and resets the carry flag and sets the AC flag.

XRA r: Ex-ORs the contents of a register with the accumulator. So, the contents of accumulator are modified. It resets both CY and AC flag.

CMP r: Compares the contents of register r with accumulator but contents of both registers are preserved. Contents of CY flag will change depending on the result. AC = unchanged.

Ex-OR of two identical values results in zero output. So, when contents of Accumulator are EX-ORed with itself then Accumulator is reset and Zero Flag is set to reflect the result.

PROG1                  MOV A, E;      A = 72H, flags unchanged

ADD L;   A = A + L = 9AH (1001 1010);  Z = 0, CY = 0

DAA;

Since, the lower nibble of accumulator is greater than 09H then 06H is added to lower nibble which makes the result A0H. Now the higher order nibble becomes greater than 09H so 06H is added to higher order nibble. Hence, A = 00H. So Carry Flag is set and zero flag is also set.

Contents of Registers,

HL = 0000H

BC = 0000H

DE = 5472H

A = 01H

CY = 0 and Z =1

CMP C: Compares the content of register C with accumulator and only flags are modified but contents of accumulator are unchanged.

CPI 3A: Compares the content of Accumulator with the data byte “3A”. The contents of accumulator remains unchanged.

ANI 5C: It is bit by bit AND operation of the data byte “5C” with the accumulator and is used for masking certain bits so it changes the contents of accumulator.

ORA A: It is a bit by bit OR operation of Accumulator with itself so the contents of accumulator are unchanged.

PUSH Instruction decrements the content of Stack Pointer by 2.

So, value of Stack Pointer after execution of each instruction is given below,

PUSH       PSW                      SP = 9FFF

XTHL                                     SP = 9FFF

PUSH       D                           SP = 9FFD

JMP          FC70                     SP = 9FFD

XTHL: exchanges top of stack with HL register pair but Stack Pointer remains same.

JMP shifts the program execution to a new address but Stack Pointer remains same.

The TRAP interrupt has highest priority followed by RST 7.5, 6.5, 5.5. Since, device A has highest priority so it must be connected to RST 7.5, B must be connected to RST 6.5 and C must be connected to RST 5.5.

The microprocessor will enter the HALT state and HALT the execution of program and releases the buses i.e. they enter tri-state logic.