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Network Analysis
Sinusoidal Steady State Analysis

Practice questions from Sinusoidal Steady State Analysis.

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Q#1 Sinusoidal Steady State Analysis GATE EE 2025 (Set 1) NAT +2 marks -0 marks

In an experiment to measure the active power drawn by a single-phase RL Load connected to an AC source through a  resistor, three voltmeters are connected as shown in the figure below. The voltmeter readings are as follows: . Assuming perfect resistors and ideal voltmeters, the Load-active power measured in this experiment, in W, is __________ (round off to one decimal place).

Explanation:

 

 

Let  be the Load pf angle.

 

 

 

 

 

 

Q#2 Sinusoidal Steady State Analysis GATE EE 2023 (Set 1) NAT +2 marks -0 marks

For the circuit shown, if , the instantaneous value of the Thevenin's equivalent voltage (in Volts) across the terminals  at time  is __________ (Round off to 2 decimal places).

Explanation:

Applying nodal analysis to super node

Diagram, schematic

Description automatically generated

∴ v(t) = 12.5 sin (1000t)

At t = 5 msec v(t) = 12.5 sin 5 = -11.986

Q#3 Sinusoidal Steady State Analysis GATE EE 2023 (Set 1) NAT +2 marks -0 marks

The circuit shown in the figure is initially in the steady state with the switch  in open condition and  in closed condition. The switch  is closed and  is opened simultaneously at the instant , where . The minimum value of  in milliseconds, such that there is no transient in the voltage across the  capacitor, is (Round off to 2 decimal places).

Explanation:

Before t = t1 Kcs open & is closed & circuit reaches steady state

Diagram, schematic

Description automatically generated

The current of 5V dc source keeps circulating in a loop & does not affect capacitor.

at t = t1,

after t = t1 k closed so ac current source is shorted &  is open so a series RC circuit with 5V dc source is formed.

Diagram

Description automatically generated

Initial capacitor voltage

Steady state capacitor voltage = 5V

Second term represents transient

For transient-free response

Q#4 Sinusoidal Steady State Analysis GATE EE 2022 (Set 1) NAT +1 mark -0 marks

An inductor having a 𝑄-factor of 60 is connected in series with a capacitor having a 𝑄-factor of 240. The overall 𝑄-factor of the circuit is ________. (round off to nearest integer)

Explanation:

When a coil a capacitor are connected in series then overall Q-factor is

Q#5 Sinusoidal Steady State Analysis GATE EE 2022 (Set 1) NAT +1 mark -0 marks

The network shown below has a resonant frequency of 150 kHz and a bandwidth of 600 Hz. The 𝑄-factor of the network is __________. (round off to nearest integer)

A picture containing diagram, sketch, line, design

Description automatically generated

Explanation:

Q#6 Sinusoidal Steady State Analysis GATE EE 2021 (Set 1) NAT +1 mark -0 marks

In the given circuit, the value of capacitor C that makes current I = 0 is _________ μF.

Explanation:

 

 Xc = 10 Ω

= 20 μF

Q#7 Sinusoidal Steady State Analysis GATE EE 2021 (Set 1) NAT +2 marks -0 marks

In the given circuit, for maximum power to be delivered to , its value should be …………… Ω. (Round off to 2 decimal places).        

Explanation:

Diagram, schematic

Description automatically generated

A picture containing text, antenna

Description automatically generated

For maximum power transfer

Q#8 Sinusoidal Steady State Analysis GATE EE 2020 (Set 1) NAT +1 mark -0 marks

Current through ammeters  and  in fig. are 1  10° and 1  70° respectively. The reading of the ammeter A1 (rounded off to 3 decimal places) is _________ A.

Explanation:

I = 1  10° + 1  70°

I = 1.732  40°

The reading of ammeter is 1.732 A.

Q#9 Sinusoidal Steady State Analysis GATE EE 2019 (Set 1) NAT +2 marks -0 marks

The voltage across and the current through a load are expressed as follows        

The average power in watts (round off to one decimal place) consumed by the load is _______.

Explanation:

For finding power, constant current to sin

Q#10 Sinusoidal Steady State Analysis GATE EE 2018 (Set 1) MCQ +1 mark -0.33 marks

In the figure, the voltages are  ,  and

. The circuit is in sinusoidal steady state, and,   and   are the average power outputs. Which one of the following statements is true?

Untitled-9.png

Explanation:

Untitled-6.png

In this problem  leads both  & hence current will flow from  towards

Hence,

Q#11 Sinusoidal Steady State Analysis GATE EE 2018 (Set 1) NAT +2 marks -0 marks

The voltage v(t) across the terminals a and b as shown in the figure, is a sinusoidal voltage having a frequency . When the inductor current i(t) is in phase with the voltage v(t), the magnitude of the impedance Z (in ) seen between the terminals a and is _______ (up to 2 decimal places).

Untitled-11.png

Explanation:

Untitled-9.png

Reactance of capacitor

Parallel combination of R & C

Total impedance

Since current & voltage have same phase. Imaginary part of impedance should be zero

Hence,

Q#12 Sinusoidal Steady State Analysis GATE EE 2018 (Set 1) NAT +2 marks -0 marks

The voltage across the circuit in the figure, and the current through it are given by the following expressions:

Where , If the average power delivered to the circuit is zero then the value of X (in Ampere) is ________ (up to 2 decimal places).

Untitled-26.png

Explanation:

For calculation of power, same frequency terms must be used in both voltage & current.

 

Q#13 Sinusoidal Steady State Analysis GATE EE 2018 (Set 1) MCQ +2 marks -0.66 marks

The equivalent impedance for the infinite ladder circuit shown in the figure is

Untitled-30.png

Explanation:

Untitled-12.png

Assume equivalent impedance = Z

Untitled-13.png

Q#14 Sinusoidal Steady State Analysis GATE EE 2017 (Set 1) MCQ +2 marks -0.66 marks

A source is supplying a load through a 2-phase, 3-wire transmission system as shown in figure below. The instantaneous voltage and current in phase-a are  V and A, respectively. Similarly for phase-b, the instantaneous voltage and current are A, respectively.         

Z:\PY\EE\Redreaw figure\Network\updated\74-66.jpg

The total instantaneous power flowing from the source to the load is

2200 W

4400 W

Explanation:

Total instantaneous power

Q#15 Sinusoidal Steady State Analysis GATE EE 2016 (Set 1) NAT +2 marks -0 marks

In the circuit shown below, the supply voltage is  volts. The peak value of the steady state current through the  resistor, in amperes, is _________________.  

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2016\EE_GATE_2016_SET_1\EE_GATE_2016_SET_1 image\22.jpg

Explanation:

The given system is shown below with two parallel LC branches marked as A and B.

D:\1Mayu\gate-14\Gate-2016\Diagrams\d-2\4.PNG

In branch A:

D:\1Mayu\gate-14\Gate-2016\Diagrams\d-2\5.PNG

Resulting parallel combination

In branch B:

Resultant parallel combination

Hence, both branches A and B will act as Open Circuit.

Now, equivalent circuit will be:

Peak value of current through

Q#16 Sinusoidal Steady State Analysis GATE EE 2016 (Set 1) NAT +2 marks -0 marks

The circuit below is excited by a sinusoidal source. The value of R, in , for which the admittance of the circuit becomes a pure conductance at all frequencies is _____________.

23.jpg

Explanation:

23.jpg

For admittance to have only conductance, imaginary part of admittance should be zero.

For resonance at all frequency is variable, so,

Note: For the circuit to be independent of frequency the time constant of both branches should be equal.

Q#17 Sinusoidal Steady State Analysis GATE EE 2016 (Set 2) MSQ +1 mark -0.33 marks

A resistance and a coil connected in series and supplied from a phase, 100V, 50Hz ac source as shown in the figure below. The rms values of possible voltages across the resistance  and coil  respectively, in volts are

4.jpg`

65, 35

50, 50

60, 90

60, 80

Explanation:

Let,

is the voltage across resistance of coil

is the voltage across inductance of coil

D:\1Mayu\gate-14\Gate-2016\Diagrams\d-2\7.PNG

Since,

Option A:

Given,

                       …………….(1)

Applying KVL in loop,

        ………….…(2)

Putting the values of in equation (2)

Putting this value in equation (1)

This means voltage across inductance = 0

This is not possible and hence option is incorrect.

Option B,

Not possible so option B is also wrong.

Option C:

Putting these values in eq (2)

Voltage across resistance can’t be negative so option C is also wrong.

Option D:

Putting in eqn (2)

This is only possible when coil is ideal but in question coil is not ideal, so this is also wrong.

Note: There is something wrong in the question and marks to all were given in this question by the GATE committee.

Q#18 Sinusoidal Steady State Analysis GATE EE 2016 (Set 2) NAT +1 mark -0 marks

The voltage (V) and current ((A) across a load are as follows.

.

.

The average power consumed by the load, in W, is_____________.

Explanation:

Current have several frequency components but voltage has only one frequency component. Average power will be due to only same frequency components.

W

Q#19 Sinusoidal Steady State Analysis GATE EE 2015 (Set 1) MCQ +1 mark -0.33 marks

An inductor is connected in parallel with a capacitor as shown in the figure.        

12.jpg

As the frequency of current i is increased, the impedance (Z) of the network varies as

13.jpg

14.jpg

16.jpg

15.jpg

Explanation:

Equivalent Impedance of Parallel RC circuit shown below is,

12.jpg

When  (inductive)

When  (capacitive)

At , impedance goes to infinity as the net admittance goes to zero. Hence, the plot of impedance versus frequency is shown below,

14.jpg

Q#20 Sinusoidal Steady State Analysis GATE EE 2015 (Set 1) NAT +2 marks -0 marks

The circuit shown in the figure has two sources connected in series. The instantaneous voltage of the AC source (in Volt) is given by . If the circuit is in steady state, then the RMS value of the current (in Ampere) flowing in the circuit is

27.jpg

Explanation:

This problem can be solved by superposition principle.

C:\Personal\GATE Guru\GATE-2015 Solutions\Session-1\Mor session\17.jpg

Solving with DC source alone by short circuiting the AC source:

In steady state, inductor is short – circuited,

Solving with AC source alone by short circuiting the DC Source:

=1,

v(t) = 12 sin t

C:\Personal\GATE Guru\GATE-2015 Solutions\Session-1\Mor session\18.jpg

By superposition theorem,

 

RMS value of i(t)

Q#21 Sinusoidal Steady State Analysis GATE EE 2015 (Set 2) MCQ +2 marks -0.66 marks

In the given network. , ,  

The phasor current i (in Ampere) is

33.jpg

Explanation:

The currents in various branches of the circuit is shown,

Z:\PY\EE\Redreaw figure\Network\updated\102-60.jpg

By KVL,

 

 

Q#22 Sinusoidal Steady State Analysis GATE EE 2015 (Set 2) NAT +2 marks -0 marks

A symmetrical square wave of 50% duty cycle has amplitude of ±15V and time period of . This square wave is applied across a series RLC circuit with  L=10mH and . The amplitude of the 5000 rad/s component of the capacitor voltage (in volt) is ____________.          

34.jpg

Explanation:

Assuming the supply voltage is represented by V (peak)

Fourier series of square wave:

 

 ms

 rad/sec

So, we are interested in fundamental.

 

Since , circuit is in resonance. Hence, fundamental current can be obtained as,

Q#23 Sinusoidal Steady State Analysis GATE EE 2014 (Set 2) MCQ +2 marks -0.66 marks

The voltage across the capacitor, as shown in the figure, is expressed as +

10.jpg

The values of and  respectively, are

2.0 and 1.98

2.0 and 4.20

2.5 and 3.50

5.0 and 6.40

Explanation:

Using super position theorem,

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\14,15,16 Images\10_1.jpg

First, open circuit current source

By Potential Division,

 =   =

Therefore,  ;  

Now, short circuit voltage source

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\14,15,16 Images\10_2.jpg

 

By Current Division,

 

Hence, =1.98 , = 78.69°

Thus, the capacitor voltage is given by,  

Q#24 Sinusoidal Steady State Analysis GATE EE 2014 (Set 2) NAT +2 marks -0 marks

The total power dissipated in the circuit, shown in the figure, is 1kW. The voltmeter, across the load, reads 200V. The value of  is ____________

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2014\Gate-EE-2014_2\EE02_2014 images\11.jpg

Explanation:

Power loss in 1Ω =  

Real Power is only consumed in resistances. Hence,

Power loss in R = 1 kW – 4W = 996W

Assuming no current goes into voltmeter i.e. ideal voltmeter,  

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2014\Gate-EE-2014_2\EE02_2014 images\11.jpg 

R = 9.96Ω

,

 

Q#25 Sinusoidal Steady State Analysis GATE EE 2014 (Set 3) MCQ +2 marks -0.66 marks

A series RLC circuit is observed at two frequencies. At , we note that source voltage   results in a current . At , the source voltage   results in a current . The closest values for R, L, C out of the following options are

Explanation:

Given,  and  

Since both the current & voltage are in phase, it is resonance condition. Under resonance condition,

Net Impedance, Z = R

R == 50 Ω

Resonance frequency, =

 

   -----------(1)        

At = 1krad/s, current is leading by an angle of 31°    

So, net impedance is capacitive.

 

= 0.6

= 50 × 0.6 = 30

From (1)

 

Since,

 

 

C = 25 μF

From (1), L = 10mH

Q#26 Sinusoidal Steady State Analysis GATE EE 2013 (Set 1) MCQ +2 marks -0.66 marks

A single-phase load is supplied by a single –phase voltage source. If the current flowing from the Load to the source is  and if the voltage at the load terminals is , then the

Load absorbs real power and delivers reactive power.

Load absorbs real power and absorbs reactive power.

Load delivers real power and delivers reactive power.

Load delivers real power and absorbs reactive power.

Explanation:

The configuration of the given system is shown below,

2.jpg

Since, the current is coming out of the positive terminal of load the load is said to be delivering power.

Complex power delivered by the load is =

Both P & Q are negative means load absorbs active power as well as reactive power from the source.

Q#27 Sinusoidal Steady State Analysis GATE EE 2013 (Set 1) MCQ +2 marks -0.66 marks

In the circuit shown below, if the source voltage  then the Thevenin’s equivalent voltage in volts as seen by the load resistance  is

D:\Vol-2\Network Analysis\SSSA-53.jpg

Explanation:

For  disconnect the load as shown below,

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\11,12,13\images\5.jpg

Q#28 Sinusoidal Steady State Analysis GATE EE 2013 (Set 1) MCQ +2 marks -0.66 marks

Two magnetically uncoupled inductive coils have Q factors  and  at the chosen operating frequency. Their respective resistances are  and . When connected in series, their effective Q factor at the same operating frequency is

Explanation:

For Coil 1,

Similarly for Coil 2,          

When connected in series,

Equivalent inductance =

Equivalent resistance =

quality factor =

Q#29 Sinusoidal Steady State Analysis GATE EE 2012 (Set 1) MCQ +1 mark -0.33 marks

In the circuit shown below, the current through the inductor is         

0 A

Explanation:

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\11,12,13\images\8.jpg

This implies that the bridge circuit is in balanced condition.        

So points A & C will be at same potential.

Due to this 1Ω resistor and j1Ω are connected in parallel.

So applying current division rule at node B.

Q#30 Sinusoidal Steady State Analysis GATE EE 2012 (Set 1) MCQ +1 mark -0.33 marks

The average power delivered to an impedance (4–j3) by a current  is

44.2W

50W

62.5W

125W

Explanation:

The current source can be represented in phasor form as,

10.jpg

Here, we are considering maximum value as the

magnitude of phasor.

        

Here, current is leading the voltage as the impedance has negative imaginary part which means that the impedance is capacitive.

Average Power,

Q#31 Sinusoidal Steady State Analysis GATE EE 2012 (Set 1) MCQ +2 marks -0.66 marks

Assuming both the voltage sources are in phase, the value of R for which maximum power is transferred from circuit A to circuit B is

19.jpg

Explanation:

13.jpg

Finding thevenin’s equivalent circuit of circuit  - B.

Open circuiting the terminals of circuit B.

14.jpg

Short the voltage source to determine the Thevenin Resistance.

                                                        

15.jpg

Representing the circuit B by its Thevenin Equivalent.

                        ----------(1)

Power transferred from A to B

For P to be maximum

Q#32 Sinusoidal Steady State Analysis GATE EE 2012 (Set 1) MCQ +2 marks -0.66 marks

23.jpg

In the circuit shown, the three voltmeter readings are .

The power factor of the load is

0.45

0.50

0.55

0.60

Explanation:

Since  is the voltage across a resistor so, it will be in same phase as current but voltage across RL load will lead the voltage by power factor angle.

The circuit and phasor diagram are shown below,

18.jpg

By Phasor Sum,

Q#33 Sinusoidal Steady State Analysis GATE EE 2012 (Set 1) MCQ +2 marks -0.66 marks

23.jpg

In the circuit shown, the three voltmeter readings are .

If , the approximate power consumption in the load is         

700W

750W

800W

850W

Explanation:

19.jpg

Given,

Power consumption in load impedance is equal to

Q#34 Sinusoidal Steady State Analysis GATE EE 2011 (Set 1) MCQ +1 mark -0.33 marks

The RMS value of the current i(t) in the circuit shown below is

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2011\GATE-Electrical-Engineering-2011 images\1.jpg

1A

Explanation:

The circuit with each element represented as Impedance as,

20.jpg

1F capacitor

1H inductor

Inductor and Capacitor cancel the impedance of each other. So,

the upper branch act as Short Circuit.

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\11,12,13\images\21.jpg

RMS value of current

Q#35 Sinusoidal Steady State Analysis GATE EE 2011 (Set 1) MCQ +1 mark -0.33 marks

The voltage applied to a circuit is   volts and the circuit draws a current of  amperes. Taking the voltage as the reference phasor, the phasor representation of the current in amperes is

Explanation:

Taking V as reference phase

Since, current lags the voltage by an angle  radians

Note: The magnitude of phasor is always rms value of the quantity.

Q#36 Sinusoidal Steady State Analysis GATE EE 2011 (Set 1) MCQ +2 marks -0.66 marks

An RLC circuit with relevant data is given below.

The power dissipated in the resistor R is

0.5W

1W

2W

Explanation:

It is given that, ,  

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2011\GATE-Electrical-Engineering-2011 images\40.jpg

The current in RL branch lags the applied voltage by 45°

Power dissipated in R resistance

P=1W

Q#37 Sinusoidal Steady State Analysis GATE EE 2011 (Set 1) MCQ +2 marks -0.66 marks

An RLC circuit with relevant data is given below.

The current in the figure above is

–j 2A

+j2 A

Explanation:

Since         

Q#38 Sinusoidal Steady State Analysis GATE EE 2009 (Set 1) MCQ +2 marks -0.66 marks

The equivalent capacitance of the input loop of the circuit shown is

Q24.jpg

2 µF

100 µF

200 µF

4 µF

Explanation:

Let us applying a voltage source at input side as shown below,

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\Network\Network\Lokesh_network_09, 10\Untitled-11.png

Applying KVL in input loop

Input impedance

Negative imaginary part of impedance shows capacitive reactance

Q#39 Sinusoidal Steady State Analysis GATE EE 2008 (Set 1) MCQ +1 mark -0.33 marks

The Thevenin's equivalent of a circuit operating at, has  and . At this frequency, the minimal realization of the Thevenin's impedance will have a

Resistor and a capacitor and an inductor

Resistor and a capacitor

Resistor and an inductor

Capacitor and an inductor

Explanation:

Since impedance has non-zero real part

So it has resistance

The impedance is having negative imaginary part. So it has overall reactance as capacitive. It may be purely capacitive or may have both capacitor and inductor having value of capacitive reactance greater than inductive reactance.

But for minimal realization of impedance a resistor and a capacitor will realize the Thevenin impedance.

Q#40 Sinusoidal Steady State Analysis GATE EE 2008 (Set 1) MCQ +2 marks -0.66 marks

The resonant frequency for the given circuit will be

Q22.jpg

1 rad/s

2 rad/s

3 rad/s

4 rad/s

Explanation:

Representing each element in terms of its impedance, the circuit can be redrawn as shown below,

Untitled-7.png        

Untitled-8.png

Impedance of parallel branch,

For resonant frequency imaginary of impedance should zero

Q#41 Sinusoidal Steady State Analysis GATE EE 2007 (Set 1) MCQ +2 marks -0.66 marks

The R-L-C series circuit shown is supplied from a variable frequency voltage source. The admittance-locus of the R-L-C network at terminals AB for increasing frequency ω is

Q62-1.jpg

Q62-2.jpg

Q62-3.jpg

Q62-5.jpg

Q62-4.jpg

Explanation:

Admittance of the circuit

At

Real part of admittance

Real part will always be positive

At

 [Maximum value]

Imaginary part of admittance

At

For

For

Untitled-5.png

So the locus of admittance looks like as shown above.

Q#42 Sinusoidal Steady State Analysis GATE EE 2007 (Set 1) MCQ +2 marks -0.66 marks

In the figure given below all phasors are with reference to the potential at point "O". The locus of voltage phasor   as R is varied from zero to infinity is shown by

Q63-1.jpg

Q63-2.jpg

Q63-3.jpg

Q63-4.jpg

Q63-5.jpg

Explanation:

Untitled-3.png

Reactance of

                

Applying KVL

When         

When         

Untitled-4.png

Hence, the locus looks like as shown above.

Q#43 Sinusoidal Steady State Analysis GATE EE 2006 (Set 1) MCQ +1 mark -0.33 marks

In the figure the current source is 10 A, R=1Ω, the impedances are , and .  The Thevenin equivalent looking into the circuit across X-Y is

Q3.jpg

Explanation:

For Open the XY terminals as shown,

Untitled-1.png

Open circuit the current source

Untitled-2.png

Q#44 Sinusoidal Steady State Analysis GATE EE 2006 (Set 1) MCQ +2 marks -0.66 marks

The circuit shown in the figure is energized by a sinusoidal voltage source  at a frequency which causes resonance with a current of I.

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2006\Figures\Q32-1.jpg

The phasor diagram which is applicable to this circuit is

Q32-2.jpg

Q32-3.jpg

Q32-4.jpg

Q32-5.jpg

Explanation:

Various resistances and impedances have been marked in the circuit shown below,

Untitled-7.png

At resonance,         

I is in phase with

At resonance

 is also in phase with  and less than

Hence the phasor diagram is,

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\Network\Network\network 2006\Untitled-8.png

Q#45 Sinusoidal Steady State Analysis GATE EE 2005 (Set 1) MCQ +1 mark -0.33 marks

The RMS value of the voltage is:

5V

7V

Explanation:

RMS of 3 volts=3

RMS of

RMS of

Q#46 Sinusoidal Steady State Analysis GATE EE 2005 (Set 1) MCQ +2 marks -0.66 marks

The RL circuit of Figure is fed from a constant magnitude, variable frequency sinusoidal voltage source . At 100 Hz, the R and L elements each have a voltage drop . If the frequency of the source is changed to 50 Hz, the new voltage drop across R is:

Q31.jpg

Explanation:

Let inductive reactance at 100Hz is

Since voltage drop across R & L is equal at 100Hz

Magnitude

RMS voltage across

Now at 50Hz

Inductive reactance=        

Current at 50Hz

RMS voltage drop across R at 50Hz=

Now from equation (4) & (2)

Q#47 Sinusoidal Steady State Analysis GATE EE 2004 (Set 1) MCQ +1 mark -0.33 marks

In the figure the value of Z in Figure, which is most appropriate to cause parallel resonance at 500 Hz, is

Q1.jpg

125.00 mH

304.20 µF

2.0µF

0.05µF

Explanation:

For parallel resonance to be happen, imaginary part of admittance of parallel network should be zero.

Since inductor is already exists. So, Z should be capacitive

Admittance of parallel network, Y=

=

For imaginary part of admittance of zero

Q#48 Sinusoidal Steady State Analysis GATE EE 2004 (Set 1) MCQ +1 mark -0.33 marks

Total instantaneous power supplied by a 3-phase ac supply to a balanced R-L load is

Zero

Constant

Pulsating with zero average

Pulsating with non-zero average

Explanation:

Load impedance

Where  &

Balanced  voltage supply

Current in the balanced  load,

Similarly,

Instantaneous power in  load ‘p’

Constant

Q#49 Sinusoidal Steady State Analysis GATE EE 2004 (Set 1) MCQ +2 marks -0.66 marks

In figure, the admittance values of the elements in Siemens are

respectively.

The value of I as a phasor when the voltage E across the elements isis

1.5 + j0.5

5 – j18

0.5 + j1.8

5 – j12

Explanation:

Untitled-4.png

Total admittance of parallel combination

        

Q#50 Sinusoidal Steady State Analysis GATE EE 2003 (Set 1) MCQ +1 mark -0.33 marks

A segment of a circuit is shown in Figure.  , . The voltage  is given by

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2003\Figures\Q2.jpg

3 – 8 cos2t

32 sin2t

16 sin2t

16 cos2t

Explanation:

Untitled-1.png

Current in resistor        

Current in capacitor

Using KCL at node ‘0’

Voltage across inductor=

Q#51 Sinusoidal Steady State Analysis GATE EE 2003 (Set 1) MCQ +1 mark -0.33 marks

In the Figure.

Untitled-2.png        .

The thevenin impedance seen from X-Y is

56.645°

6030°

7030°

34.465°

Explanation:

For thevenin impedance short circuiting the voltage source

Untitled-2.png

        

Q#52 Sinusoidal Steady State Analysis GATE EE 2003 (Set 1) MCQ +2 marks -0.66 marks

In the circuit of Figure, the magnitudes of  and  are twice that of . The inductance of the coil is Q31.jpg        

2.14 mH

5.30 H

31.84 mH

1.32 H

Explanation:

Given,

By using KVL in circuit

Untitled-3.png

In a series RLC circuit, the inductor and capacitor voltage are out

of phase.

Hence,

So the circuit is at resonance

Hence

Quality factor of circuit

Since

Q#53 Sinusoidal Steady State Analysis GATE EE 2002 (Set 1) MCQ +2 marks -0.66 marks

In the circuit shown in Figure, what value of C will cause a unity power factor at the ac source?

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2002\Figures\Q27.jpg

68.1 µF

165 µF

0.681 µF

6.81 µF

Explanation:

Untitled-2.png

Admittance of capacitor                

Admittance of combination

Total admittance of parallel combination

For unity power factor at source end

Imaginary part of admittance should be zero.

Q#54 Sinusoidal Steady State Analysis GATE EE 2002 (Set 1) MCQ +2 marks -0.66 marks

A series R-L-C circuit has R = 50Ω, L = 100 μH and C = 1 μF. the lower half power frequency of the circuit is

30.55 kHz

3.055 kHz

51.92 kHz

1.92 kHz

Explanation:

Resonance frequency

Hence

Q#55 Sinusoidal Steady State Analysis GATE EE 2002 (Set 1) MCQ +2 marks -0.66 marks

Consider the circuit shown in Figure. If the frequency of the source is 50 Hz, then a value of  which results in a transient free response is

Q37.jpg

0 ms

1.78 ms

2.71 ms

2.91 ms

Explanation:

For transient free response

Power factor angle

This is based on the concept that if we switch ON at the time corresponding to lagging angle between voltage and current then current starts from 0 and it follows steady state current so there is no transient.

If we switch ON when the steady state current is non-zero then transients are induced.

Q#56 Sinusoidal Steady State Analysis GATE EE 2002 (Set 1) NAT +2 marks -0 marks

An electrical network is fed by two ac sources, as shown Figure. Given that ,  and .  Obtain the Thevenin equivalent circuit (Thevenin voltage and impedance) across terminals x and y, and determine the current  through the load .

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2002\Figures\Q53.jpg

Explanation:

To determine the Thevenin Voltage, the load terminals must be opened as shown below,

Untitled-6.png

Applying KVL in loop

To determine Thevenin Impedance, both voltage sources must be shorted as shown below,

Untitled-7.png

Thevenin equivalent circuit:

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\Network\Network\network 2002\Untitled-8.png

= 0A

Q#57 Sinusoidal Steady State Analysis GATE EE 2001 (Set 1) MCQ +1 mark -0.33 marks

In a series RLC circuit at resonance, the magnitude of the voltage developed across the capacitor.

Is always zero

Can never be greater than the input voltage

Can be greater than the input voltage, however, it is 90° out of phase with the input voltage.

Can be greater than the input voltage, and is in phase with the input voltage.

Explanation:

Current in series RLC circuit is,

78.jpg

Under Resonance Condition,

         (in phase with voltage source)

Voltage across capacitor

if ; then = so  can be greater than voltage source and  is  phase behind the source voltage.

Q#58 Sinusoidal Steady State Analysis GATE EE 2001 (Set 1) MCQ +2 marks -0.66 marks

A 240 V single-phase ac source is connected to a load with an impedance of .  A capacitor is connected in parallel with the load.  If the capacitor supplied 1250 VAR, the real power supplied by the source is

3600 W

2880 W

2400 W

1200 W

Explanation:

Real Power will only be absorbed by Load and not by Capacitor.

Q#59 Sinusoidal Steady State Analysis GATE EE 2001 (Set 1) MCQ +2 marks -0.66 marks

Determine the resonance frequency and the Q-factor of the circuit shown in figure.

Data: R = 10Ω, C = 3µF, ,  and M = 10 mH.

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-2001\Figures\Q51.jpg

f=430.52Hz and Q=10

f=530.52Hz and Q=5

f=530.52Hz and Q=10

f=530.52Hz and Q=20

Explanation:

Assuming currents and voltages on both sides the system is shown below

88.jpg

Since,         ---------(1)

                ---------(2)

Since output side is short circuited, so

                        ---------(3)

From equation 1 & 3

When

Resonance Frequency

Quality factor

Q#60 Sinusoidal Steady State Analysis GATE EE 2000 (Set 1) MCQ +2 marks -0.66 marks

The impedance seen by the source in the circuit in figure, is given by

D:\Vol-2\SSSA-19.jpg

Explanation:

The given system is shown below,

72.jpg

Referring load impedance

’ to primary side

Equivalent circuit becomes as shown below,

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\Network 91-01\Network Images\73.jpg

Impedance seen by source,

Q#61 Sinusoidal Steady State Analysis GATE EE 2000 (Set 1) NAT +2 marks -0 marks

Predict the current I in figure in response to a voltage of  . The impedance values are given in ohms. Use the thevenin’s theorem.

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\Network 91-01\Network Images\74.jpg

Explanation:

To determine Thevenin equivalent across the 10Ω resistor, the resistor must be open circuited as shown below,

75.jpg

By voltage divider rule

Zth across  resistor, the voltage source is short circuited,

76.jpg

So, Thevenin equivalent circuit is shown below,

77.jpg

Q#62 Sinusoidal Steady State Analysis GATE EE 1999 (Set 1) MCQ +1 mark -0.33 marks

The current in the circuit shown in figure is:

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-1999\images\Q1_1.12.jpg

5A

10A

15A

25A

Explanation:

Since,

55.jpg

but voltage across capacitor are opposite in phase.

So, net effect of capacitor and inductor cancels out. Circuit is under resonance.

Q#63 Sinusoidal Steady State Analysis GATE EE 1999 (Set 1) MCQ +2 marks -0.66 marks

A fixed capacitor of reactance –j0.02 kΩ is connected in parallel across a series combination of a fixed inductor of reactance j0.01 kΩ and a variable resistance R. As R is varied from zero to infinity, the locus diagram of the admittance of this L-C-R circuit will be

A semi-circle of diameter j 100 and center at zero

A semi-circle of diameter j 50 and center at zero

A straight line inclined at an angle

A straight line parallel to the x-axis

Explanation:

The arrangement in the question is shown below,

65.jpg

Admittance         

When R = 0

When R = 0.01

= 50 S

When         

So the locus of Y looks like as shown below,

66.jpg

It is a semi-circle of diameter j100 and center at zero.

Q#64 Sinusoidal Steady State Analysis GATE EE 1999 (Set 1) MCQ +2 marks -0.66 marks

The voltage phasor of a circuit is  and the current phasor is A. The active and the reactive powers in the circuit are:

10W and 17.32 VAr

5W and 8.66 VAr

20W and 60 VAr

and

Explanation:

Given voltage source,

Supply Current,

Complex power

Q#65 Sinusoidal Steady State Analysis GATE EE 1998 (Set 1) MCQ +1 mark -0.33 marks

A sinusoidal source of voltage V and frequency f is connected to a series circuit of variable resistance, R and a fixed reactance, X. the locus of the tip of the current-phasor I, as R is varied from 0 to ∞ is:

A semicircle with a diameter of

A straight line with a slop of

An ellipse with  as major axis

A circle of radius   and origin at  

Explanation:

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\Network 91-01\Network Images\44.jpg

Current

Since ‘X’ is fixed and ‘R’ is variable

When R = 0;

When R = X;

When ;

So the locus of I will ok like as shown below

45.jpg

So the locus of I is a semicircle with diameter

Note: In such type of questions, the process followed is similar to drawing Polar Plot in Control Systems.

Q#66 Sinusoidal Steady State Analysis GATE EE 1998 (Set 1) MCQ +1 mark -0.33 marks

A circuit with a resistor, inductor and capacitor in series is resonant of  If all the component values are now doubled, the new resonant frequency is:

still

Explanation:

Let initially resistance, capacitance & inductance is R, C & L respectively and resonant frequency is .

Now, new resistance, capacitance & inductance

R’ = 2R

C’ = 2C

L’ = 2L

New resonant frequency

Hence,

So, resonance frequency is halved.

Q#67 Sinusoidal Steady State Analysis GATE EE 1998 (Set 1) MCQ +1 mark -0.33 marks

A series R-L-C circuit when excited by a 10V sinusoidal voltage source of variable frequency, exhibits resonance at 100Hz and has a 3 dB bandwidth of 5Hz. The voltage across the inductor L at resonance is:

10V

200V

Explanation:

Quality Factor,

Voltage across inductor at resonance= 20 x 10= 200Volt

Q#68 Sinusoidal Steady State Analysis GATE EE 1996 (Set 1) MCQ +1 mark -0.33 marks

A water boiler at home is switched on the a.c. mains supplying power at 230V/50Hz. The frequency of instantaneous power consumed by the boiler is

0 Hz

50 Hz

100 Hz

150 Hz

Explanation:

Power consumed by boiler =

where V = voltage across boiler =

Here,

Note that 230V is rms value of the supply voltage

R = resistance of Boiler circuit coil

Where

Hence frequency of P is 100Hz

Note: The instantaneous power in a single phase AC Circuit oscillates at twice the supply frequency.

Q#69 Sinusoidal Steady State Analysis GATE EE 1996 (Set 1) MCQ +2 marks -0.66 marks

A coil (which can be modeled as a series RL circuit) has been designed for high-Q performance at a rated voltage and a specified frequency. If the frequency of operation is doubled, and the coil is operated at the same rated voltage, then the Q-factor and the active power P consumed by the coil will be affected as follows

P is doubled, Q is halved

P is halved, Q is doubled

P remains constant, Q is doubled

P is decreased 4 times, Q is doubled

Explanation:

Since Q- factor of series RL circuit =

When frequency is doubted,

Hence, Q is doubled.

Active power,

Current in a RL Series Circuit is given by,

Since,         ,

Since coil is having high quality factor. So,         

 

So P decreased by 4 times.

Q#70 Sinusoidal Steady State Analysis GATE EE 1995 (Set 1) NAT +1 mark -0 marks

A series R-L-C circuit has the following parameter values: , , .The Q factor of the circuit at resonance is __________

Explanation:

        25.jpg

Since resonant frequency,

Quality factor of series RLC circuit =

Q#71 Sinusoidal Steady State Analysis GATE EE 1995 (Set 1) MCQ +2 marks -0.66 marks

In the network system shown in figure, find the current through  using nodal method. The values of voltages are given in volts and the impedances are given in ohms.

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Typed\Gate-EE-1995\images\Q10.jpg

Explanation:

The given network is,

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\Network 91-01\Network Images\30.jpg

Applying KCL at node ‘

Current through

 

Q#72 Sinusoidal Steady State Analysis GATE EE 1994 (Set 1) MCQ +1 mark -0.33 marks

At resonance, the given parallel circuit constituted by an iron-coil and a capacitor behaves like

Z:\PY\EE\Redreaw figure\Network\updated\67-05.jpg

An open-circuit

A short-circuit

A pure resistor of value R

A pure resistor of value much higher than R

Explanation:

The phasor diagram for the given circuit is shown below,

21.jpg

At resonance, only in phase component of current remains so that power factor should be unity.

Hence, quadrature component of current must cancel out.  

Total Current,   

 is the impedance angle of ‘R - L’ branch.

The current in RL branch would be,

        

Since

Total impedance 

Since, the power factor is unity the impedance will be resistive.

Q#73 Sinusoidal Steady State Analysis GATE EE 1994 (Set 1) NAT +1 mark -0 marks

In the given circuit, the voltage , has a phase angle of _____________ with respect to .

Explanation:

Inductor voltage can be calculated using Potential Divider,

22.jpg

Hence,  leads  by 60°.

Q#74 Sinusoidal Steady State Analysis GATE EE 1993 (Set 1) MCQ +1 mark -0.33 marks

The following circuit (figure) resonates at

D:\1Mayu\Gate-9\JPG\JPG\1\1993\Q_6_2.JPG

all frequencies

0.5 rad/sec

5 rad/sec

1 rad/sec

Explanation:

Impedance of circuit

19.jpg

For resonance, imaginary part of impedance = 0

Hence,

Q#75 Sinusoidal Steady State Analysis GATE EE 1992 (Set 1) MCQ +2 marks -0.66 marks

Currents , and   meet at a junction (node) in a circuit. All currents are marked as entering the node.

If  and , then  will be

Explanation:

The arrangement of three currents entering a node is shown in the figure,

64.jpg

Using KCL at node ‘A’

Q#76 Sinusoidal Steady State Analysis GATE EE 1992 (Set 1) MCQ +2 marks -0.66 marks

A constant voltage frequency sinusoidal voltage source of magnitude  is connected to a series circuit made of a resistance of 15Ω, a coil of winding resistance R and inductance L and a 50μF capacitor. The voltage across the 15Ω resistors is 30V, across the coil is 50V, across the capacitor is 40V, The voltage across the combination of the 15Ω resistor and the coil together is 72.11V. Determine the values of the inductance L, winding resistance R and the source voltage V.

L=0.01H, R=15Ω  and V=60V

L=0.02H, R=30Ω  and V=60V

L=0.02H, R=15Ω  and V=30V

L=0.02H, R=15Ω  and V=60V

Explanation:

The circuit configuration for the data given is shown below,

C:\Users\Ankit\Dropbox\GATE papers\EE papers\Solutions\network\Network 91-01\Network Images\68.jpg

                        --------------(1)

        --------------(2)

The voltage across resistance R and 15Ω is in phase and voltage in Inductor is 90° leading with respect to resistor voltage.

From equation 2

Since,

Put the value of ‘R’ & ‘ω’ in equation 2

Q#77 Sinusoidal Steady State Analysis GATE EE 1991 (Set 1) MCQ +1 mark -0 marks

In the figure shown,  are ideal ammeters. If  read 5 and 13A respectively, reading of  will be

Z:\PY\EE\Redreaw figure\Network\updated\67-01.jpg

8A

12A

18A

Indeterminate unless the actual values of R, C and  are specified

Explanation:

3.jpg

The phasor diagram for parallel RC circuit is shown below,

4.jpg

 &  are  in phase        

                

                

        

Hence, reading of 2nd ammeter,         

Q#78 Sinusoidal Steady State Analysis GATE EE 1991 (Set 1) MCQ +2 marks -0.66 marks

A one port active network has an input admittance Y, the magnitude of which is shown in figure as a function of frequency. The circuit is resistive or capacitive in different frequency ranges.

Complete the following table:

Frequency Range

Type of Impedance

Value (Ω/H/F)

10000 rad/sec < ω

A

P

10 rad/sec < ω < 1000 rad/sec

B

Q

D:\Vol-2\SSSA-03.jpg

A= Capacitive, P=C=10μF and B=Inductive  Q=L=0.01H

A= Capacitive, P=C=100μF and B=Inductive  Q=L=0.1H

A=Inductive  P=L=0.01H and B=Capacitive  Q=C=100μF

A= Capacitive, P=C=100μF and B=Inductive  Q=L=0.01H

Explanation:

The plot of admittance Vs frequency is shown below,

D:\1Mayu\Gate-9\JPG\JPG\1991\q 2.6    1991-Model.jpg

The admittance of various circuit elements is,

In dB the admittance is given by,

As the magnitude of admittance is constant between, the impedance would be resistive.

The admittance has a negative slope between, the impedance is inductive and its value at  is 20dB

L = 0.01 H

The admittance has a positive slope between, the impedance is capacitive and its value at   is 0dB

C = 100μF

Q#79 Sinusoidal Steady State Analysis GATE EE 1991 (Set 1) MCQ +2 marks -0.66 marks

In figure calculate

Z:\PY\EE\Redreaw figure\Network\updated\67-03.jpg

(a) The power delivered by each source

(b) The power dissipated in each resistor

(a) -j4.33, 7.5 +j4.33 (b) 4.5, 3

(a) -4.33, 7.5 +j4.33 (b) 4.5, 5

(a) -j4.33, 7.5 +j4.33 (b) 5.5, 3.5

(a) -j4.33, 8.5 +j4.33 (b) 5.5, 3

Explanation:

(a) -j4.33, 7.5 +j4.33 (b) 4.5, 3)

7.jpg

Based on Transformation Ratio,

  and         

Applying KVL in loop 1                        

                  ………(1)        

                             ………..(2)        

Applying KVL in Loop 2                        

       ………(3)        

Substituting the values of  and

                     ………(4)        

Adding equation 2 & 4         

(a)        Power delivered by source (1)

Power delivered by source (2)  

(b) Power dissipates in 6Ω resistor  = 4.5 Watt

Power dissipates in 16Ω resistor