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Q#1
Logic Family
GATE EE 2006
MCQ
+2 marks
-0.66 marks
A TTL NOT gate circuit is shown in figure. Assuming VBE = 0.7V of both the transistors, if Vi = 3.0 V, then the states of the two transistors will be
ON and 
OFF
reverse ON and OFF
reverse ON and ON
OFF and reverse ON
Explanation:
In TTL Logic, if the input is high then the Transistor Q1 is in Reverse Active Mode and when input is low then the Transistor is in Forward Active Mode. In reverse active mode, the current flows from emitter to collector and turns ON the transistor Q2.
Q1 reverse ON and Q2 is ON.
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