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Q#1
Logic Family
GATE EE 2005
MCQ
+2 marks
-0.66 marks
If X1 and X2 are the inputs to the circuit shown in figure, the output Q is:
Explanation:
This is a digital logic implemented using NMOS Transistors.
When X1 is high the output X is connected to ground
so, X = 0 and when X1 is low then the PMOS transistor
pulls the output X to 1. So, the first logic acts as Inverter.
In the second logic gate when either X or X2 is high then the output is pulled low to logic 0. So, the second logic gate is NOR gate.
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