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Q#1
Sequential Circuits
GATE EE 2000
MCQ
+2 marks
-0.66 marks
The counter shown in the figure, is initially in state 
. With reference to the CLK input, draw waveforms for 
and P for the next three CLK cycles.
None
Explanation:
The preset input to Q0 & Q1 flip flop is such that flip flop will be set when clock & Q2 will be high or logic ‘1’.
The waveforms for the output are shown below assuming that all the Toggle inputs are high.
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