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Q#1
Sequential Circuits
GATE EE 2015
NAT
+2 marks
-0 marks
The figure shows a digital circuit constructed using negative edge triggered J – K flip flops. Assume a starting state of 
. This state will repeat after __________ number cycles of the clock CLK.
Explanation:
The state table for the system shown is given below,
So, original state is reached after 6 clock cycles.
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